FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5875 Discussions

FIR Compiler output is zero

Honored Contributor I

I have a design that is using a FIR Compiler generated FIR filter containing several coefficient sets. To be exact I had 5 sets loaded into the FIR filter. Everything was working fine. Then I tried to add a 6th set and now the output I get from the filter is all zeros even though I use one of my previous filter sets.  


When the output is all zeros the output format is still correct. I verified this with SignalTap.  


I was wondering if anyone has seen anything like this.
0 Kudos
1 Reply
Honored Contributor I

I found the problem myself. Looks like the FIR compiler is scaling all the coefficient sets with the same factor. This means that you can't mix floating and fixed point coefficient sets. I just converted the fixed point set to floating point and things started working.