Hi,
I am trying to get a PAL output form the clocked video out core using embedded sync. This is supposed to be fairly straight forward, but for some reason I just cannot get it to work. My setup is as follows:
Test Pattern Generator -> Clocked Video Output.
The SOPC system clock is 50MHz and the video output clock 27MHz. I have setup the TPG with the following parameters:
Frame Width: 720
Frame Height: 576
Data Width: 8 bits
Interlaced (F0 first)
4:2:2 colour bars with colour planes in seqeunce.
I have setup the CVO with the following parameters:
I have loaded the PAL preset and changed the bits per colour plane to 8-bits. Apart from that I have not changed anything.
What I see is that my TV cannot sync to the image. I have looked the embedded sync codes (F,V and H) and found that the F field is not toggling as expected 50 times per second. It is high for two consecutive fields (going low only during the vertical blanking period) and then low for one field, then high for two fields and low for one field again. I monitor the FIFO UF and it never underflows. This is about as simple a system as is possible! I have also generated the BT.656 stream with a simple state machine to check my video encoder, and it works. So the problem must lie within the FPGA.
The embedded syncs are obviously created incorrectly and there must be some parameter that I have set incorrectly. Anyone who has been a working PAL with embedded syncs that can shed some light?
Thanks!
Niki
