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Altera_Forum
Honored Contributor I
1,675 Views

PCI-Express Reference Design on Cyclone IV GX Transceiver Starter Kit

Hi, 

 

I am looking for a simple PCI-e reference solution on Cyclone4 GX. If I'm not wrong, so far all the demo design are done on the Stratix IV GX and Arria II GX developement board.  

 

Question: 

(1) Is there any simple demo for PCI-e on the Cyclone4 GX starter board? 

 

(2) Can the simple design in Stratix IV/Arria II GX developement board be port into the Cyclone4 GX board?
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4 Replies
Altera_Forum
Honored Contributor I
33 Views

you can start off with design example generated when you instantiate PCIe core.

Altera_Forum
Honored Contributor I
33 Views

We have come across a number of people who need a more complete solution and so have put together our own reference design which we will be selling for around £40. 

 

The MEV Altera Cyclone IV PCIe Reference Design Kit includes Quartus reference designs for Altera Cyclone IV PCIe designs and is targeted for the Altera Altera cycloneIVGX 4cgx15 development kit and the EBV Altera cycloneIV db4cgx15 development kit  

 

It has been developed as a starting point for customers own designs and includes  

· A working "MEV Altera Cyclone IV PCIe debug device" device and driver that can be deployed on a development kit for quick proof of concept OR to user hardware check hardware is OK  

· Hardware design source code as a starting point for a users own design  

· A Windows debug driver for this device. The Windows Debug driver and API library allows arbitrary registers to read and written on the debug device whether it is deployed on the above kits or an equivalent design deployed on user hardware.  

 

It will be up on our web page soon www.mev.co.uk (http://www.mev.co.uk

If you are interested get in touch
Altera_Forum
Honored Contributor I
33 Views

Altera_Forum
Honored Contributor I
33 Views

There is a PCIe master mode example there which is based on the PCI express wizard generated example code and not an SOPC. The example is based on a PCI express complier version < 10.1 and the serdes fixed clock is derived from the PCI Ref Clock, which is not recommended in Altera PCI express Compier user guide. I am not sure if this may cause issues. 

 

Ours is a simple PCIe slave on the SOPC so it is easy to reconfigure to suit user designs built in Quartus 10.1