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Altera_Forum
Honored Contributor I
993 Views

PCI express Stratix IV implementation

Hi there, 

 

I'm using a Stratix IV GX and i want to use the PCI express link to transmit data from my FPGA to another one. The data which have to be sent are generated by a personnal IP and no need for me to read or write in memory. What i want to do is connect my IP to the PCIe IP in order to give it the data but without passing trought the Avalon bus. 

Regarding this and after reading some documentations about PCIe implementation i have few questions: 

 

- Does the sending FPGA has to be in root port or can i implement both FPGA as endpoints?  

- Is it better or easier to use the " PCIe Soft IP" or the "PCIe Hard IP" ? (most of the exemples are about the Hard IP) 

- Can i directly interface my signals to those from the PCIe IP without passing trought the Avalon bus ? ( I think that yes it may possible but i haven't found any exemple of it, so i don't really know if it can be done easily). 

 

Sorry if i'm asking very basics questions but i'm a little bit lost with all i have seen. :) 

 

Thank you. 

Best Regards, 

Alexis
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4 Replies
Altera_Forum
Honored Contributor I
29 Views

Have you considered using the Avalon streaming interface? its just a fifo interface then. But you will need a copy of the PCIe spec as you will need to create all of the TLP packet headers yourself. Its not too complicated, but you have to ensure you cope with all the rules. Have you read the user guide?  

 

http://www.altera.co.uk/literature/ug/ug_pci_express.pdf 

 

It does make mention of a physical layer interface, but I dont think I would want to go into that without a lot of time on my hands.
Altera_Forum
Honored Contributor I
29 Views

Hey tricky, 

 

Thanks for your reply i take your advice but if it's possible i'd rather not use the avalon bus.:) 

Yes i went trought the user guide, and i have seen that a "descriptor/data" can be configured instead of the avalon interface. It may be my solution don't you think ?  

I have generated the vhdl files of the PCIexpress Soft IP using this "descriptor/data" with Mega Wizard and now i'm looking at all the I/O signals of this IP. 

I supposed that i have to link a lot of them and not only "tx_data, tx_desc, rx_data, rx_desc", what do you think ?  

But by the way, i had to configure BAR registers in mega wizard but i don't think that i need them since i don't want to work with any "memory location". 

 

Thank you for any advice. 

Best, 

Alexis
Altera_Forum
Honored Contributor I
29 Views

I have only use the streaming bus before - worked well for me. 

Good luck with your work - let us know how it goes.
Altera_Forum
Honored Contributor I
29 Views

Well ok thanks:) 

I 'm going to try with the descriptot/data and see how it goes. I'll let you know if I succeed by doing so. 

 

Best, 

Alexis
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