FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

PCIE 128 PCIE core

Honored Contributor II



I have an issue while using Altera's 128-bit PCIE core. I connected 128-bit(4x) pcie endpoint with 64-bit (1x) pcie rootport. After configuring PCIE core  


1. I send a read TLP from Root to end point (No issue) 

2. Sends completion from End point (No issue, received correctly) 

3. Sends another read TLP exactly same as previous with different TAG. (No issue) 

4. Sends completion from End point exactly same as previous but with different TAG ID (didn't received at root side


The actual problem is whenever i send completion TLP from Endpoint, the endpoint core gets stucked i.e. all TLPs followed by that completion never reached the opposite end or in some scenarios tx_ready gets de-asserted forever. Interesting point is my first completion always received correctly at rootpoint. But after that pcie end core stops responding. 


Plz guys, guess what the issue can be??? 


Thanks in advance
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Honored Contributor II

Maybe you’re not terminating the first completion correctly, so the PCIe block hangs and cannot transport your second completion? 


– Matthias
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