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PCIE CHANGE SPEED

ALega1
Beginner
432 Views

Good morning, I've a design pcie For Arria 10 based on the IP PCIE SRV-IO gen3 x8. I would like to reconfigure the link speed to 5.0g after FPGA configuration. After some research, I've found the reg specification for hip_reconfig interface on the arria 10 pcie core. After booting we proceed with the access to this register us your timming specification on image :
"Figure 6.6 Hard IP Reconfiguration Bus Timing of Read-Only Registers"
of Arria 10 Avalon-MM Interface document paraph Hard IP Reconfiguration Interface.
After accesing to register, we read the content from address 0x8 and ahead instead from 0x89.

0x89 15:0 Vendor ID. 0x1172
0x8A 15:0 Device ID. 0x0001
7:00x8B Revision ID. 0x01
0x8C 15:0 Class code[23:8]. —
0x8D 15:0 Subsystem vendor ID. 0x1172
0x8E 15:0 Subsystem device ID. 0x0001
0x8F — Reserved. —
0 Advanced Error Reporting. b'0
0x90
3:1 Low Priority VC (LPVC). b'000
7:4 VC arbitration capabilities. b'00001
15:8 Reject Snoop Transaction. b'00000000

 

We also write the register 0x00 to '0' for enable the writes on that memory area.

After write any value the BIOS cant find the new value. (Including reseting BIOS without FPGA reconfiguration, the value on the bus is correctly written and readed).
This bus is doing nothing on the pcie enumeration, why??? Something missundertood. We need to do something with the (test_in signals??)

After some effords we find also an option on the core instanciation called: speed_change_hwtcl, and under the installation repository, appears to be the next files:

vlog "../../vhd/core_reconfiguration/altpcie_hip_eq_bypass_ph3.v" -work altera_pcie_a10_hip_180
vlog "../../vhd/core_reconfiguration/altpcie_sc_bitsync.v" -work altera_pcie_a10_hip_180
vlog "../../vhd/core_reconfiguration/altpcie_sc_dprio_rd_wr.v" -work altera_pcie_a10_hip_180
vlog "../../vhd/core_reconfiguration/altpcie_sc_dprio_seq.v" -work altera_pcie_a10_hip_180
vlog "../../vhd/core_reconfiguration/altpcie_sc_hip_vecsync2.v" -work altera_pcie_a10_hip_180
vlog "../../vhd/core_reconfiguration/altpcie_sc_lvlsync.v" -work altera_pcie_a10_hip_180
vlog "../../vhd/core_reconfiguration/altpcie_sc_lvlsync2.v" -work altera_pcie_a10_hip_180
vlog "../../vhd/core_reconfiguration/altpcie_sc_dprio_top.v" -work altera_pcie_a10_hip_180
vlog "../../vhd/core_reconfiguration/altpcie_sc_ctrl.v" -work altera_pcie_a10_hip_180

This core connects internally to the hip_reconfig_* interface, and also seams to we writting a new speed on the core but its done on an unspecified address d181???

localparam DPRIO_CTRL_REG_2_TLS = 10'h2;
localparam DPRIO_CTRL_REG_111_CSEB = 10'd111;
localparam DPRIO_CTRL_REG_181_EN_SPD_CHG = 10'd181;

could you please provide a memory map for that register on the hard pcie ip?? Is posible to renegotiate the speed after device is configured?. Thanks in advance and best regard.

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8 Replies
skbeh
Employee
403 Views

The Hard IP reconfiguration interface only can be used to reconfigure the read-only register. For instance, use this interface to modify the device ID register at run time. It cannot be used to change the pcie link speed from Gen3 to Gen2.
Users need to set the intended link speed during IP parameterization, recompile Quartus to get the .sof, then reconfigure the device.

ALega1
Beginner
404 Views

Hello, we can't modify the deviceID either, could you provide some example? We just want to enumerate to the BIOS a maximun speed of gen2. We can do it from intel BIOS, but this option is not available for AMD processor, and we would like to change the value of maximun speed supported.

 

Thanks in advance and best regards.

skbeh
Employee
388 Views

A10 user guide below at section '5.7.1. Hard IP Reconfiguration Interface' has the description and timing diagram of hip_reconfig_* interface.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf#pag...

skbeh
Employee
387 Views

May I know what is your intention to modify the deviceID? Is that you want to try using the hip_reconfig* interface to modify the deviceID, after that use the same interface/method to also modify the speed_change_hwtcl to change the pcie link speed?

ALega1
Beginner
378 Views

Good morning, first of all, first of all,  the memory map is missed on the paper!!! "https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf#pag..." We have the signals description, but nothing about the addressing of that bus!!!!, or some information about the register to be read or write????. We have found an memory map on UG-01145_avmm, but the address doesnt fit with the data readed on the real core (we use Signal Tap to see all the content on the bus). The fisrt word vendor id is readed from address 0x08 intead form address 0x89!!! And so on (everything seem to be offset from address 0x89 to address 0x8???? how is that possible? Could you provide the internal memory map of the hard IP for pcie???). We just modify the device id to test the interface its workuing, but not working properly. The BIOS always read the original value, no the written througth the reconfiguration interface. We also tried to write the register 0x9F, we try to modify the PCie Capability Version from compliant PCIe Specification 3.0 to PCIe Specification 2.0, in order to force BIOS to enumerate our device as a gen2 compliance. On pcie standard there is register called Link Capabilities Register, for enumeration of supported bandwith and Link width, there is any chance to be mofied from that interface?? We attach our user code and also the UG-01145. Thanks in advance and best regards.

skbeh
Employee
374 Views

You can use below procedures to dynamically reprogram the register:
1) Bring down the PCIe link by asserting the hip_reconfig_rst_n reset for a few cycles, ser_shift_load and interface_sel stay high during this period. npor is driven low, and stays low throughout the process.
2) After reconfig_rst_n go high (enter user mode), make sure ser_shift_load and interface_sel stay high for 324ns, as per the Figure 34 timing diagram in the A10 user guide.

3) After waiting 324ns for PLL to locked, drive ser_shift_load low for 4 cycles, then high, while interface_sel stays high.
4) After 4 more cycles, drive interface_sel low.

5) Assert hip_reconfig_write for four cycles, with hip_reconfig_address set to 0, and hip_reconfig_writedata set to 0.
(Write to location 0 of value 0, to enable PCIe reconfig mode. When 0, PCIe reconfig mode is enabled.
When 1, PCIe reconfig mode is disabled and the original read-only register values set in the programming file used to configure the device are restored.)

6) Assert hip_reconfig_write for four cycles, with hip_reconfig_address set to 0009h (instead of 0x8A), hip_reconfig_writedata set to the desired new device ID (i.e. 0xb500).

7) Read from register 0009h as the address for device ID.
Expect the device ID after 4 clock cycles. (npor reset signal is released).

ALega1
Beginner
365 Views

The BIOS is not detecting the new Device ID, even with your timming, I send you attached the signal tap capture (the capure clock is 8 ns). We suposed that the pin_perst should not be on reset (there is not info on its status), we connect the pin perst direcly to pcie reset.  We can writte and read the registers and everything looks good, but the enumeration from BIOS side side is still the old one.

 

Thanks in advance and best regards.

skbeh
Employee
355 Views

pin_perst resets the PCI Express datapath and control registers. Should be asserted for a minimum of 100ms at power-on by the system controller.
npor is a function of both pin_perst and local reset, but resets the entire IP core, PCS, PMA and PLLs. Should be asserted for a minimum of 20ns or 10 clock cylces.
Typically perst is the "system reset", npor is the "local reset".

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