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PCIE HIP msi_request occurring before the corresponding avalon stream

ASvir2
Beginner
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Hi everyone,

 

I'm using pcie hip in a multifunction design (I have 2 functions).

 

Due to difference in propagation delay of the Avalon stream TLPs and the msi interrupt requests in the app layer of my FPGA design, there's sometimes a situation where app_msi_request reaches pcie HIP before the corresponding Avalon stream TLP (it's a matter of ~20 clk).

 

Could this be an issue for the pcie hip?

 

Thank you.

 

 

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Nathan_R_Intel
Employee
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Hie,

 

Could you help clarify your question a little more. Are you saying the write TLP is ~20 clock cycles after app_msi_req? This could be dependent on when app_msi_tc and app_msi_num has a valid window.

Hence, this might not be entirely dependent on the PCie HIP.

The following wiki side has some timing diagram related to app_msi_req.

 

https://fpgawiki.intel.com/wiki/Handling_PCIe_Interrupts

 

 

Regards,

Nathan

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