Hi,
I'm using the PCIE example design for the Avalon Streaming port on the Cyclone V. It's running PCIE Gen 2 and so has a 128-bit interface. I'm trying to get a large descriptor table used, and on the whole it works, but a few quirks I have noticed, and they are causing me some grief now:
1) It does two FIFO Descriptor Table reads for each descriptor entry - but the FIFO is 128 bits wide, so it only needs to do 1. This means every descriptor entry needs to be duplicated.
2) Every 256 entries (128 real entries) it reads from the wrong memory, and actually uses the entry from 256 lines earlier. I can adjust the table so that every 256th entry points to the PC memory 256 lines further ahead, and that works, except the 0th entry needs to be adjusted for the first incorrect line, and I can't adjust that.
3) As it gets close to the end of the table, it rereads the start rather than continuing to the end. Why?
For reference, the table is now 4320 entries long.
Any help would be greatly appreciated.
Cheers,
Simon
