FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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PCIe BAR Addressing in QSys Design

Honored Contributor II


I have successfully simulated "PCI Express Hard IP end point design with Qsys" in QII 11.0.  

We are following the same configuration except that our root port is a DSP (our endpoint is Cyclone IVGX).  

It has onchip memory and DMA. The Qsys design has BAR 0:1 as 64 bit prefetchable and targeted to access on chip memory; but Qsys address map shows 32 bit addressing (0x00200000 - 0x00200fff) which is around 4KB;  

1) should this be 64 bit addressing?  

2) It also has BAR2 as 32-bit non-prefetchable targeting CRA and DMA.  

I have following address mapping:  

- onchip_memory_0.s1 (bar 1_0) = (0x00200000 - 0x00200fff)  

- pcie_hard_ip_0.cra (bar2) = (0x00000000 - 0x00003fff)  

- dma_0.control_port_slave = (0x00004000 - 0x0000403f)  

3) the guys at the rootport side want the final addresses, and I am not able to tell them the final BAR addresses based on the above info.  

4) Address translation table if required has to be done on endpoint side or root port side?  



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