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PCIe Compiler IRQ Handling SOPC

Honored Contributor II



I have a question about the handling of the IRQs by the PCIe Compiler from Altera. Espacially what is happening if there is more then one Interrupt at a time. 


First of all I can see a single IRQ signal (RXmlrq_i) coming to the core with a specific IRQ number. 

( I have to route them by hand after generation of the SOPC-Builder http://www.altera.com/support/kdb/solutions/rd08032010_560.html (http://www.altera.com/support/kdb/solutions/rd08032010_560.html)) 


pcie_compiler_0_Rx_Interface_irq <= IRQ_0 or 

IRQ_1 or 



If one of the three IRQs is coming from the local side the number is updated in the IRQ number Register (RXmIrqNum_i [5:0]). 


pcie_compiler_0_Rx_Interface_irqnumber <= std_logic_vector'("000000") when IRQ_0= '1' else 

std_logic_vector'("000001") when IRQ_1 = '1' else 

std_logic_vector'("000010") when IRQ_2 = '1'; 


My question is about the handling with multiple IRQs. 



IRQ_0 has been shown at the core. The register is filled with "000000". The Host is reading the AVL_IRQ_INPUT_VECTOR from the configuration space of the pcie_compiler. Before he can do that, IRQ_2 is signaled and the value in the Register is changed to "000010". So we can say, IRQ_0 is lost. 


Is that a possible scenario? At this point I can not see any mechanism to store the single IRQs one after another. But if there is one, my next question would be, how is the priority handling realized? 


Thank you in advance for your answers!
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