FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

PCIe Config Fails Intermittently

Altera_Forum
Honored Contributor II
‎09-17-2010 02:42 PM
876 Views

I have an ArriaGX design with a PCIe Gen1 x4 using the Altera PCIe IP. About one in 50 times, Windows does not see the board during configuration. The PCIe traffic that I see is the normal link init, then the Config Read. The FPGA responds with an ACK about 40-45milliseconds later but there is no completion. The PC continues to try to read the config and then gives up. This happens on a reboot without a power cycle so I don't think it is related to loading the FPGA. 

 

I am in the process of adding logic to observe the test_out port. 

 

Has anyone seen anything similar?
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.