FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5890 Discussions

PCIe Config Fails Intermittently

Honored Contributor II

I have an ArriaGX design with a PCIe Gen1 x4 using the Altera PCIe IP. About one in 50 times, Windows does not see the board during configuration. The PCIe traffic that I see is the normal link init, then the Config Read. The FPGA responds with an ACK about 40-45milliseconds later but there is no completion. The PC continues to try to read the config and then gives up. This happens on a reboot without a power cycle so I don't think it is related to loading the FPGA. 


I am in the process of adding logic to observe the test_out port. 


Has anyone seen anything similar?
0 Kudos
0 Replies