I have an ArriaGX design with a PCIe Gen1 x4 using the Altera PCIe IP. About one in 50 times, Windows does not see the board during configuration. The PCIe traffic that I see is the normal link init, then the Config Read. The FPGA responds with an ACK about 40-45milliseconds later but there is no completion. The PC continues to try to read the config and then gives up. This happens on a reboot without a power cycle so I don't think it is related to loading the FPGA.
I am in the process of adding logic to observe the test_out port. Has anyone seen anything similar?