Hello Everyone,
I have following Agilex FPGA design requirements.
- PCIe x16 Endpoint with BAR size of minimum 8K - I have dependency that BAR 0 offset 0 to 8K must be reserved for my application specific usage. Offset above 8K is free.
- Host to Device (H2D) and Device to Host (D2H) DMAs. - DMAs are totally controlled by custom HW login inside FPGA. Based on BAR0 accesses from host side; Device would make its own descriptors and other control signal to Initiate H2D and D2H DMAs. This DMA transfer could be variable lengths.
I am reviewing Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide and specifically External Descriptor Controller option as my staring point - https://www.intel.com/content/www/us/en/docs/programmable/683517/25-1/external-descriptor-controller-72769.html
Here is the block diagram for example design from the webpage
I find that this example design is the closet to PoC design I want to create. I need more help in understanding the External Descriptor Controller Example design so that I can figure out where and what can I change to meet my design needs. I have following questions to begin
- While following steps to generate design example using quartus/platform designer, I see that BAR 0 is chosen to be 4MB. While analyzing design In platform designer I see that DUT (blue box in figure 22 above)dut.po_bam_master port is connected to BAM_interpreter (grey box in figure 22 above)BAM_INTERPRETER_M0.AVMM_BAM_SLAVE port and address mapping is 0x0 to 0FFF_FFFF (256MB) which is greater than 4MB BAR0.
- I want to understand how current design is using 256MB of space. can you help?
- What offset is used for what purpose ?
- Are BAR0 (4MB) accesses are mapped to "BAR interpreter" (grey box) in above figure 22? If yes, what 4MB range between 256MB address range is mapped to BAR0?
- How BAR0 4MB space is used? What offset is used for what purpose ?
- While analyzing design In platform designer I see that DUT (blue box in figure 22 above)dut.po_h2ddm_master port is connected to DMA_MEM (grey box in figure 22 above)DMA_MEM_M0.AVMM_H2DDM_SLAVE port and address mapping is 0x1_0000 to 1_7FFF (32KB) . Similarly, dut.po_d2hdm_master port is connected to DMA_MEM (grey box in figure 22 above)DMA_MEM_M0.AVMM_D2HDM_SLAVE port and address mapping is 0x1_0000 to 1_7FFF (32KB) .
- What is the reason here to have starting offset as 0x1_0000 for both AVMM connections? I mean the address ranges could also be 0x0 - 0x7FFF; but so what is the reason behind choosing address range 0x1_0000 to 1_7FFF?
- In platform designed when I click on DMA_MEM_M0 it shows an IP which I am not quite familiar with. But it feels like that it is Dual ported RAM. My question is can I replace DMA_MEM_M0 with Dual ported RAM IP (2 AVMM slave ports and Ip Configured for 32KB memory) without breaking example design functionality ?
- I see that the example design has generated some driver and application code and https://www.intel.com/content/www/us/en/docs/programmable/683517/25-1/external-descriptor-controller-03941.html has steps on how to use it. However I need detailed documentation on driver and application which could explain Flow diagrams of inner workings like - how device is initialized, how driver buffer are allocated, how DMA descriptors are created and loaded into DMA, how the data is actually transferred between host memory and Device memory (DMA_MEM and/or other memory/registers inside FPGA), how completions or acknowledgement is sent etc. can you point me to this level of details? Understanding all this will help me towards how can I take this base driver and application, and modify them to fit into my
thank you and looking forward to this journey
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