PCIe - DMA - External Descriptor Controller Example - question set 2

[UserID4331231]

this is a second part question after https://community.intel.com/t5/FPGA-Intellectual-Property/PCIe-DMA-External-Descriptor-Controller-Example/m-p/1701684#M30648 

Continuing next step of question on DMA transfer between Host and Device memory. https://www.intel.com/content/www/us/en/docs/programmable/683517/25-1/external-descriptor-controller-72769.html  has three sections   "Descriptor Fetch operation" , "H2D Data movement operation", and "D2H Data movement operation". It also has table 20 which has host descriptor format.

I have following question on host descriptor format.

1. I understand that for both D2H and H2D  the format is same. I want to understand more details on the 64 bit address fields.
   1. Will this pointer address be 64 bit virtual address  ? Basically, the device driver /app running on host can reserve some buffer in host memory and Virtual address belonging to that buffer needs to be used here. Is this correct understanding?
      1. Will this pointer address be 64 bit AVMM address which is mapped to AVMM agent port on the "DMA_MEM"?
1. For Source address and Destination address, for pointer which belongs to Host memory
   1.  For Source address and Destination address, for pointer which belongs to Device memory or "DMA_MEM"
2. What does WB_EN bit 177 does? What does enabling write back mean for H2D and D2H transfers? Can you explain in details.

I have following questions around  sections   "Descriptor Fetch operation" , "H2D Data movement operation", and "D2H Data movement operation".

1. In platform designer I see that d2hdm* and h2ddm* interfaces are AVMM-ST interfaces. Which is used for point- to point communication between two design modules. However information regarding what exact packet format is exchanged on each interface and what does each field means in that packet is  missing. Can you provide these information?
1. For example  - during fetch commands on h2ddm_desc interface, what does fetch command looks like ? What  are each byte and what does it mean? Can you provide example waveforms to understand what typical exchange looks like and what are special cases which needs to be supported?
2. And same way when Descriptors from H2D Descriptor Queue are pulled out, translated to corresponding data mover commands, and sent to MCDMA through h2ddm_desc interface; what does fetch command looks like ? What  are each byte and what does it mean? Can you provide example waveforms to understand what typical exchange looks like and what are special cases which needs to be supported?

2.    I understand that in this current example design the descriptors are  created by application/driver running on the host. 1st the descriptors are fetched from host memory to H2D/D2h Queues in device using data movers. And then descriptors are fetched from queues and appropriate DMA command is sent to data movers so data can be moved  from H2D or D2H.

1. In my use case-  I don’t need to fetch descriptor from host memory as HW logic inside device is capable of generating descriptors (as per table 20 which has host descriptor format mentioned. ) What interface, protocol and packet format I need to use to submit descriptors to  H2D Desc queues and D2H Desc queues inside DUT/MCDMA IP?   

[RongYuan]

Hi,

After reviewing, these questions require more detailed investigation. Please kindly contact your local FAE/DFAE or create an IPS for this.

Thanks,

Rong