Question about TXS interface of the PCIe IP core (AVMM) for Cyclone 10 GX

[Derek_Teng]

Hi

Regarding the txs_address_i[w-1:0] of the TXS interface of the PCIe IP core (AVMM) for Cyclone 10 GX, the user manual states: "Address of the read or write request from the external Avalon-MM master. This address translates to 64-bit or 32-bit PCI Express addresses based on the translation table. The value is determined when the system is created."

In addition, it also states: "Note: The PCI Express-to-Avalon-MM bridge supports both 32- and 64-bit addresses. If you select 64-bit addressing the bridge does not perform address translation."

When I instantiate the PCIe IP core and set the Avalon-MM address width to 64-bit, the parameters "Number of address pages" and "Size of address pages" will not appear. Instead, there is "Address width of accessible PCIe memory space". The value of w in txs_address_i[w-1:0] is equal to the value of the parameter "Address width of accessible PCIe memory space".

My questions are:

When I choose to set the Avalon-MM address width to 64-bit, is the address on txs_address_i equal to the address of the PCIe domain to be accessed?

If so, do I need to set the "Address width of accessible PCIe memory space" to 64?

If I don't set it to 64, then txs_address_i cannot cover the 64-bit address.

If the PCIe core does not perform address translation, how can it obtain the 64-bit PCIe domain address through this address that is less than 64 bits?

In addition, it should be noted that my PCIe address is 64-bit.

[TanmayK_Altera · Accepted solution]

When I choose to set the Avalon-MM address width to 64-bit, is the address on txs_address_i equal to the address of the PCIe domain to be accessed?
Yes. When the Avalon-MM address width is configured to 64 bits, the value presented on txs_address_i is sent directly as the PCIe address for the transaction. The bridge performs no address translation.

If so, do I need to set the "Address width of accessible PCIe memory space" to 64?

Yes, if you need to access the full 64-bit PCIe address space, you must set the "Address width of accessible PCIe memory space" parameter to 64.

If I don't set it to 64, then txs_address_i cannot cover the 64-bit address.

If you configure the "Address width of accessible PCIe memory space" to be less than 64, then txs_address_i cannot represent the entire 64-bit PCIe address range. Only a subset of the PCIe address space will be accessible.

If the PCIe core does not perform address translation, how can it obtain the 64-bit PCIe domain address through this address that is less than 64 bits?

 If the Avalon-MM address width or the "Address width of accessible PCIe memory space" parameter is less than 64 bits, so only a partial range of the PCIe address space can be accessed. To access the full 64-bit PCIe address space, both parameters must be set to 64.

Let us know if you have any further doubts.

References:

• Arria® 10 or Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide
  • Section 3.2, "Avalon-MM Settings"
  • Section 5.1.5, "Non-Bursting Slave Module" (for signal widths)
• Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide 
  • Appendix A.4.8, "PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge"