Intel P-tile Avalon ST BAR0 addr_offset

[Adithiya_R]

 Hi Everyone, I am using Ptile-pcie ip in endpoint mode, Gen4 1x8 256 bit configuration and Quartus 23.4

• I have an issue regarding bar0_write with a different offset.
• I tried the following tlp [Data_width 32 byte]
  • FMT_type                :-    Mem_wr_3Dw 
  • Dword                      :-     1 
  • First_be                   :-      F
  • Last_be                   :-      0
  • Address offset      :-      4
• In address offset  4, I expect the valid data to be positioned at the 4th to 7th byte instead, it follows the 0th to 3rd byte location. 

Whatever the address offset, I provide the data is always starts at the 0th position. Is it how actually P-tile Ip design? 

[ventt]

Hi Adithiya_R,

Thanks for reaching out.

Allow me some time to investigate your issue. I shall come back to you with the findings.

Thanks.

Best Regards,

Ven

[ventt]

Hi Adithiya_R,

Are you running it on a testbench simulation or conducting hardware testing? How do you set the BAR0 offset? Could you please share the waveform that captures the observation?

Thanks.

Best Regards,

Ven

[Adithiya_R]

Hi Ventt
     I found that these issues are because the design supports Address alignment mode, but the Pcie ptile ip  default mode is Dword_align mode . Is there a provision to change this to "address_align"  mode ?

[ventt · Accepted solution]

Hi Adithiya_R,

Thanks for sharing your observation.

This is an expected behavior. The TLP header and data are dword aligned. There is no workaround to change the address alignment that I am aware of.

If you use the BAM and BAS modes on P-Tile, the AVMM address is aligned to the natural width of the data. For example, if the data width is 64B, the addresses must align to 64B.

Thanks.

Best Regards,

Ven

[ventt]

Hi Adithiya_R,

May I know if you have any further inquiries on this forum? 

If there are no further inquiries, I will transition this thread to community support.

Thanks.

Best Regards,

Ven

[Adithiya_R]

Hi Ventt 
      We are trying to run ptile pcie in end_point mode + user_logic, but during timing analysis "coreclkout_hip" the one generated by HIP ( hard pcie_ip core) and fed to user_logic , is not visible in the "all clocks report" 

what would be the procedure to enable this?

In Gen 3 1x8 256 bit with 250 Mhz mode, Quartus is not able to automatically detect this "coreclkout_hip" and do the timing analysis of user_logic that's synchronous with respect to this clock  

[ventt]

Hi Adithiya_R,

Thank you for confirming the answer provided.

Could you please create a new forum post about the new inquiries on the clock and timing analysis?

We prefer to have separate issues or inquiries filed for each distinct support issue to ensure better tracking and resolution.

Since the initial inquiries on the P-Tile AVST BAR have been addressed, I will transition this forum to community support.

Thank you for your understanding.

Thanks.

Best Regards,

Ven

[ventt]

Hi Adithiya_R,

I am glad that your questions have been addressed.

With that, I will transition this thread to community support. If you have a new question, feel free to open a new thread to get support from Altera experts.

Thanks.

Best Regards,

Ven