PCIe DMA write posted or non-posted

[MateuszZ]

Hello, 

i have question about intel PCIe driver for (in this case) Cyclone 10 devices. 
When using DMA, FPGA becomes master of operations. After completing its job, it sends interrupt with MSI message. 
From what i understand non-posted TLPs are re-transferred when crc error is detected (on hardware level). Read operations are always non-posted. 

What type of messages FPGA uses when it tries to write data to processor?
When we send MSI interrupt? After completing posted write transfer or after getting confirmation about completion of non-posted transfer? 

Second question - if i get crc error with posted message, will driver corrupt my data in device memory? (just to confirm )

Is there any difference when using other device families (+ Agilex 5)? 

Thanks for help
Mateusz

[Harshx]

Hi,

Thanks for contacting Intel. I'm assigned to support request.

I'll investigate on this case related and get back to you soon once I have any finding.

Thanks for your patience.

Best regards,

Harsh M

[Harshx · Accepted solution]

What type of messages FPGA uses when it tries to write data to processor?

Posted Write Transactions.

Ref: 3. Intel® Arria® 10 or Intel® Cyclone® 10 GX Parameter Settings

When we send MSI interrupt? After completing posted write transfer or after getting confirmation about completion of non-posted transfer? 

Posted write case: No acknowledgement -> MSI is not directly tied to the completion -> no completion needed

Non Posted case: acknowledgement TLP -> Once TLP received initiator can send an MSI interrupt

Conclusion: MSI are sent after the completion.

[Harshx]

Second question - if i get crc error with posted message, will driver corrupt my data in device memory? (just to confirm )

No (Transmission error-> crc error is detected -> corrupted TLP packet is discarded -> No data is written to the memory.)

Is there any difference when using other device families (+ Agilex 5)? 

Yes, Agilex 5 supports link speed upto 4.0 (cyclone 10 upto 2.0 only) different FPGAs have different Capabilities and varies in terms of performance, speed, number of transceivers availability [Vary with Tiles (F-tile, P-tile, H-tile, R-tile,etc)]

Check: PCIe* Intel® FPGA IP