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PCIe EndPoint IP

Honored Contributor II



I am considering to use Altera's FPGA together with some of its IP blocks but I need some guidance and clarifications before I can decide whether it is suitable for my usages: 


PCIe EndPoint IP Queries1 : 

- Can I configure the PCIe EndPoint not to return any Completion so that I can synthesize the Completion myself; this is including Configuration Type 0 which is targeting the PCIe EndPoint's Config Space?  

- Can I do the above while instantiating the PCIe IP Transaction Layer instead of trying to redesign the entire Transaction Layer? If yes, then how can I achieve this?  

- Can I do the above with either Hard IP and Soft IP; or only Soft IP? 


PCIe EndPoint IP Queries2 : 

- I want to store all the TLP which is received by the PCIe EndPoint into the On-Chip RAM (which has a NIOS II processor). This is because I need the NIOS II processor (applicable software) to process each TLP before returning the Completion for corresponding Non-Posted TLPs. Can I design a block inside the PCIe Endpoint Transaction Layer to push all the TLP to the On-Chip Memory or there is an IP that Altera already have that could perform such flow?  

- If I need to design my own DMA, how can I do that? Any reference to the documentation or anyone I can discuss in details especially the interface protocol with other RTL blocks, etc? 

- If there is a more robust method provided by Altera, can you enlighten me about this? 


Thanks in advance.
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