FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

PCIe Endpoint Memory

Altera_Forum
Honored Contributor II
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Hi All, 

In the Altera PCIe high performance reference design, reads and writes to the FPGA endpoint go to the DPRAM (altsyncram). There is one port for read, one port for write. Is there any easy way to copy this data out of the DPRAM and into the FPGA application logic, such as another RAM? Is there any easy way to copy data back into this DPRAM? Thanks.
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