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Altera_Forum
Honored Contributor I
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PCIe Endpoint requester

Hi all, 

 

What i want to do here is just a simple thing and i'd like to have your advices before to start. 

I want to make a point to point PCIe communication between an EndPoint and a Root. 

The Endpoint is a Stratix IV GX and the Root a computer on linux or windows xp. 

 

 

I want the Endpoint to send data or read data from the root via PCIe. 

 

- End point side : 

I'll use Altera PCIe Hard IP on the FPGA but should i configured it in Legacy or Native Endpoint? 

I have read that only legacy can initiate I/O transactions but i have also read that both (legacy and native) can do so. So i'm a little bit confused. 

 

I'll use an avalon st interface but without passing trought the avalon bus, my application layer will take care of it and link directly the proper signals (rx_st_data, rx_st_valid,tx_st_data, tx_st_valid...). 

 

I also may not use the BARs and create my own memory area (list of resgisters) to stock the data sent by the root during memory read. Is that feasible ? 

 

My aplication layer will handle the TLP header creation for read and write. 

To know the address space of the root as well as its ID, have i to read on its configuration register before starting the read and write requests ? 

 

- Root side : 

On the root side i have several choices. 

1- I have seen a post in Altera forum (i cannot put the link because my numbers of post has to be at least 5) where in the zip file there is a program which allows to access the PCI board from Linux. But i have to see if i can perform endpoint request to the root with it. And this program is made for a Qsys design on FPGA side so i have also to see if it can fit with MegaWizard PCIe Hard IP. 

 

2- Write my own drivers 

 

3- Maybe someone knows a software application (on linux or windows xp) or have a code that i can use in order to perform data read or write from FPGA to the computer. 

 

What can you advice me ? 

 

Any comments is welcomed! 

Thanks a lot. 

 

Best, 

Alexis
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Altera_Forum
Honored Contributor I
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PS: Attached is how i plan to make FPGA side

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