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Altera_Forum
Honored Contributor I
739 Views

Phase alignment reference using ALTPLL and ALTPLL_RECONFIG modules

Hi, 

 

My system contains a PLL linked to a PLL Reconfig module driven by a microcontroller via the Avalon-MM port. 

 

I used the AN661 PDF (altera.com/literature/an/an661.pdf Page 4 and 5) to understand the PLL Reconfig module interface and program it. 

 

I obtain the desired frequencies but I don’t manage to obtain a zero degree phase. 

 

The Phase related register at address 000110 is a write only reg and permits to shift the phase from the current value of the phase, am I right ? 

How can I know the current phase ? How can I align my outputs clocks to the VCO or the input clock ? 

I just want to align the low to high edge of my two output clocks (c1 = c0 / 8). 

 

Thanks for your help, 

 

Romain.
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Altera_Forum
Honored Contributor I
51 Views

First, a correction : for ArriaV family it's not ALTPLL any more, but ALTERA_PLL IP. 

Then in the ALTERA_PLL User Guide, it is explained that the pin reset, just reset counters and locked state, not the whole PLL and its config. 

So now, I apply the reconfig, then I reset PLL, and the clocks are all aligned.
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