FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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DDR2 SDRAM Controller with ALTMEMPHY signals

Honored Contributor II



I am using the DDR2 SDRAM Controller with ALTMEMPHY ip core. I received a reference design that I am basing my design from. What is the external_connection signal? In the reference design it is not hooked up to anything or exported. This produces a warning. Can someone tell me what the signal is for? 


The memory conduit is what is exported and connected to the sdram.  


Thank you for any help you can provide.
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