FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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PCIe-Ethernet Bridge help

Honored Contributor II



I am working with Arria V GT and want to make standard Ethernet controller like Intel 82599. 

So, i have correct PCS block (tested) and want to use 2 IP cores - Avalon MM DMA for PCI Express and Ethernet MAC. They was tested individually, but i have some problem in building the whole system.  

There are 2 Avalon ST signals after Ethernet MAC IP, but DMA IP for PCIe use Avalon MM interface to onchip_memory(RAM). Have any idea, how can i connect Avalon ST data from MAC and RAM with Avalon MM interface. Maybe i need 2 another DMAs(modular MM-to-ST and ST-to-MM) to connect Avalon ST(from MAC) and RAM. Or maybe this memory is unnecessary generally and i can use DMA directly form Avalon ST to PCIe? And, how can i get statistics how much Ethernet packets lost in DMA transaction? Please, help me with any ideas. 



Thanks all!
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Honored Contributor II



We are also working on similar type of design on Cycleon V FPGA Board to access SD Card through our custom SDHC Host Controller which has one DMA Controller for PCIe-SD Bridge Inteface. Now, I want to read/write data from/to SD Card through my Linux PCie Driver using Chaining DMA. 


Do I need to connect DMA Read & Write Master Port to one of BAR region from FPGA design to read/write data on SD Card from Linux System? or Can I Directly use DMA without assigning into any BAR Region? 


Please let me know if anyone has idea about that. 



Ritesh Prajapati
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