FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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PCIe HIP AVMM for cyclonev

Honored Contributor II

Good morning, 

I'm using a PCIe Hard IP AVMM for cyclonev in my design: the IP is connected to a RAM through Avalon Memory Mapped Interface. 

The testbench environment has been created by Qsys and includes the driver, which provides the reset signal (pin_perst) together with the signals on the serial pins (tx_0 and rx_0). The rtl simulation is working fine, and the RAM is written and read correctly. 

Moreover, I compiled my design in Quartus II 14.1, generating both the post synthesis netlist and the post fit netlist succesfully. 


Now I'm testing the post synthesis netlist, but I see that the PCIe testbench is not working on it. The link stays in DETECT.ACTIVE and DETECT.QUIET, until the simulation fails because no communication has been established. 

Has anybody faced this kind of issue? 




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