Hi all,I'm new to FPGAs and I want to make a new component in qsys. I saw the ip for Optrex 16207 LCD controller core and there also another in "altera\15.0\ip\altera\sopc_builder_ip\altera_avalon_lcd_16207". But I want to learn how to do this myself. I'm doing an LCD because I have code I've written before and I know how it works. Right now this looks very complicate but I don't have an active project and I have time. I'm using the BeMicro MAX10 for this and Quartus 15.0.1. I've read the documents for the avalon interface and the examples to make new components but this is going to take me some time. The first question is how to convert all the# defines in the code to an equivalent in IP/FPGA design. Like 4-bit vs 8-bit interface. Will this be part of the tcl file? How fancy can the wizard get? Can I have a picture of an LCD and have the user decide 4-bit vs 8-bits and says the number of chars and lines the LCD will have? Do I need to get the tcl/tk for this? Thanks
You can display parameters and have the user configure them. Not sure you can do anything graphical (i.e. picture of the LCD).What do you mean by# defines? Sounds like C code not HDL. Or do you mean the `define statements in Verilog? Really you should be using parameters in HDL rather than `defines. The parameters can then be displayed in Qsys and the user set the values (these will be embedded into HDL code generated by Qsys).
The# defines come from the c code of the lcd. I guess in Verilog they'll be parameters? What about the physical interface of 4-bits vs 8-bits? I'd like something like a radio button in the wizard when I add the new component to a system that will enable say 4-bits and disable 8-bits (and vice versa). Is that possible?Thanks