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PCIe Hard Micro related Signals

Altera_Forum
Honored Contributor II
1,113 Views

Hi All 

 

about the DUT transmitter interface to PCIe_HM. When DUT transmits data on transaction interface, which signal can be used to indicate that lower word is valid or not? The signal rx_st_be0 is for receiver interface. 

 

Looking forward for your response. 

Thanks in advance
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Altera_Forum
Honored Contributor II
102 Views

If you are using a 128-bit AV-ST interface, the tx_st_empty signal indicates whether or not the upper 64-bits contain any valid data or not. Finer granularity is determined by address and length.

Altera_Forum
Honored Contributor II
102 Views

Byte enables are part of the TLP, there is a »first DW BE« and a »last DW BE« field in the header. Look at a Section called » First/Last DW Byte Enables Rules« in your PCI Express Specification. 

 

rx_st_be0 is an optional convenience signal introduced by Altera for received packets only, you could equally decode and use first/last DW Byte Enables of the received TLP. Upon transmission you can only set byte enables based on the mentioned TLP fields.
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