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Hi All,
We had several successful designs with PCIe IP Compiler on Cyclone IV GX using SOPC Builder and Qsys. Now we decided to make our own designs with the same core in Verilog. I am examining the user's manual of this core and have a lot of questions about it. Maybe these are basics but are not clear for me. I understand the basic core has Avalon ST interface which transfers the PCIe header also. So a stream interface should be built up which decodes it. But it contains several field. Where can I get information about these fields in the system during runtime? The IDs? How is the addressing done during runtime? Do this interface give physical addresses? How should I know if my internal modules are addressed or not? The appendix of the manual does not give any information about these questions. Where are the control registers of this core? In SOPC Builder/Qsys they are available through the CRA port but here how are they mapped? Are these information included in the manual? I did not find. I do not know where to start and need for help. Regards, IstvanLink Copied
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I suggest reading the PCI and PCIe Specs from the PCI-SIG. Those clearly state what to do in reaction to a received TLP and how to construct transmit TLPs. The Altera PCI Express User Guide just tells you how you interface these TLPs with the Avalon-ST interface.
You might get a first impression looking at this article (http://billauer.co.il/blog/2011/03/pci-express-tlp-pcie-primer-tutorial-guide-1/), continued here (http://billauer.co.il/blog/2011/03/pci-express-tlp-pcie-primer-tutorial-guide-2/). That is a very brief introduction to the topic, alongside with a lot of advertisment for the author’s solution (Xillybus) which I can neither recommend nor discourage to use because I don’t know it. At least it might be hard to make it work on Altera because it seems to be written solely for Xilinx FPGAs. – Matthias- Mark as New
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I recommend you get a copy of the mindshare PCIe system architecture. You can buy the ebook version for $32
http://www.mindshare.com/learn/?section=11e3067e0ba2- Mark as New
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Hello Matthias and Tricky,
Thanks for the responses! Now I am reading the PCIe specs and many things turned to be clear. We will buy books also for better understanding. Best regards, Istvan
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