PCIe MCDMA Gen3x16 Simulation Descriptor Size limits

[Chellambalaji]

Hi,

I am using Quartus20.3 tool to generate example design for PCIe_MCDMA gen3x16.

After that i ran the simulation inside the path "project_name/pcie_ed_tb/pcie_ed_tb/sim/synopsis/vcs".

Default test is working fine for bytecounts 4092. Tests are written in the altpcietb_bfm_rp_gen3x8.sv inside the path  "pcie_ed_tb/ip/pcie-ed_tb/DUT_pcie_tb_ip/altera_pcie_s10_tbed_191/sim" .

I modified the bytes_count as 8192 bytes and payload size in single descriptor from 2KB to 4KB.

Found the DMA write(H2D) was working fine and in DMA read D2H found the data integrity error.

I will attach the snapshots of modified bfm file. Kindly check and reply.

[Chellambalaji]

Hi 

I attached the bfm file altpcietb_bfm_rp_gen3x8.sv  snapshots. Kindly check this and reply.

[Chellambalaji]

Hi team,

I attached the snapshots. kindly help me to  solve this.

[Chellambalaji]

Hi team,

I debugged using waveform found the h2d and d2h ports having same data, but in Root Port bfm memory the data mismatches. We checked out of 8192 bytes , 7300 bytes are matched remaining bytes are written as 'h00 in memory. So kindly reply that BFM having any limitation in descriptor size or how to modify  this dma test to work properly?

Regards,

Chellambalaji

[BoonT_Intel]

Hi Sir,

I am sorry to say that the BFM is provided on an as-is basis, we can't provide any support to modify it.