Hello,
I am using the Altera PCIe IP core with the Avalon-MM interface. The FPGA is acting as master and requests a read. In SignalTap I can see that it puts the address and asserts the read enable signal. However, it then receives a Wait Request signal. This signal is never deasserted.
On the PC side, I am using the Jungo WinDriver and Windows XP. When the FPGA is master and is performing a write, there is no problem.
Any thoughts as to what could be the cause?
Thank you,
$g
