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PCIe Master does not receive any data

Altera_Forum
Honored Contributor II
804 Views

Hello, 

 

I am using the Altera PCIe IP core with the Avalon-MM interface. The FPGA is acting as master and requests a read. In SignalTap I can see that it puts the address and asserts the read enable signal. However, it then receives a Wait Request signal. This signal is never deasserted. 

 

On the PC side, I am using the Jungo WinDriver and Windows XP. When the FPGA is master and is performing a write, there is no problem. 

 

Any thoughts as to what could be the cause? 

 

Thank you, 

 

$g
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1 Reply
Altera_Forum
Honored Contributor II
75 Views

Hi, 

 

I started a topic about a similar issue a while ago: 

http://www.alteraforum.com/forum/showthread.php?t=31439 

 

This is a very similar issue. Or possibly the same. Which type of motherboard do you use for testing? 

 

Please let me know if you find something. I will do the same. 

 

Regards, 

Istvan
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