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PCIe P-Tile avalon RX header address insights

Karthik30
Beginner
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Hi in the P-Tile Avalon in the RX part only lower 6 bits of address is use.
1. Is it a byte address or dword address.
2. If an byte address then how only 6 bits can take byte address greater then 128 bytes in case of 128 MPS and 256 bytes to transfer.
#1st data will be passed with the initial address offset. #2nd data with initial offset+128 byt adress which will eventually go out of 7 bit boundary?

Thank you
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Wincent_Altera
Employee
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Hi,


in the P-Tile Avalon in the RX part only lower 6 bits of address is use

>> sorry i do not get your question, may I know what is the current gen speed that you are running ?

>> where you get the 6 bits address that you acquired from ? is there mentioned in the user guide ? appreciate you can redirect, just to ensure we are looking at the same picture.

>> may i know specific which rx header that you are looking at ?


If you are referring to the header width, you may check below

https://www.intel.com/content/www/us/en/docs/programmable/683059/24-3/overview-56727.html


Regards,

Wincent_Altera




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Wincent_Altera
Employee
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Hi,

I wish to follow up with you about this forum thread.

Hoping to hear back from you so that we can proceed for next step.

Regards,

Wincent


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Wincent_Altera
Employee
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Hi,

As we do not receive any response from you on previous question/reply/answer that we provided. Please login to “https://supporttickets.intel.com/s/?language=en_US’, view details of ddesire request, and post a feed/response within net 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on follow-up questions.

Regards,

Wincent_Altera


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