PCIe User guide Avalon Stream for Cyclone V readyLatency of RX Interface inconsistent

[Smarty]

Hi all,

the user guide Cyclone V Avalon Streaming Interface for PCIe Solutions (UG-011110_avst)  says in the Revision history that the treadyLatency was changed to 3 cycles (2019.01.18 Version 18.0). But throughout  the document the RX latency is always mentioned to be 2.

What is true ? I assume the revision history is wrong, but I am not sure.

Any help ?

[BoonT_Intel · Accepted solution]

Hi Sir,

I check internally, the correct readylatency for the RX is 2. You are right, the revision table needs to be corrected.

[Smarty]

This answers my question,

Thanks !

[BoonT_Intel]

Welcome. We already feedback to the document owner and it will be amended in a future release.