PCIe Verification IP (for Cyclone V Gen2 x 4)

[LastHorizon0711]

Hi there, 

I am fiddling around with a PCIe design on a Cyclone V. This is just for personal use. I am looking for a way to simulate it but what I don't have is any PCIe host side verification IP that I can use in my testbench for my FPGA design to talk to. I believe this means my simulation of my PCIe interface is just sat in Link Training mode and nothing else is happening. 

Does anyone know either: 
a) where I can get some simulated PCIe IP for free? 

b) How to set up my testbench correctly? 

I will happily provide any further information (just don't want to clog this post up unnecessarily!) 

Many thanks! 

[skbeh]

Hi Sir

For PCIe simulation, you can refer to Chapter 2 of below user guide.

Follow these steps to generate the testbench from the example design and run the simulation using Modelsim.

The example designs include scripts to compile and simulate the Cyclone V Hard IP for PCI Express IP Core.

Cyclone V Avalon Streaming (Avalon-ST) Interface for PCIe Solutions User Guide

https://www.intel.com/content/www/us/en/docs/programmable/683524/18-0/datasheet.html