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Hi,
We have A10 GX devkit with us and I want to get started with PCIe testing and example designs.
I have windows 10 Host PC.
Please suggest on how do I get started with PCIe?
Example design is good way to start with or any other things I can get to try it before to have fair understanding.
Is there any example design which I can run and is supported in Windows 10, I could only see most designs with Linux. Some designs it does mention as windows but doesn't specify which windows version. Can you pls confirm?
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Hi,
You can try to use AN708 that is available for Windows.
- 64-bit Windows driver and application.
- In the package, there is a word document which explains how to install the driver,
- what additional software needs to be installed, and how to run the application.
You may try to run it, if there have any problem, feel free to reach back to us.
Regards,
Wincent_Intel
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Hi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
Regards,
Wincent_Intel
p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.
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Hi ,
The frequency of the clock, you may refer to the user guide
https://cdrdv2-public.intel.com/666787/ug_a10_pcie_avmm-683724-666787.pdf
But it depends on which design that you are using either is AVST, AVMM , MCDMA ?
Regards,
Wincent_Intel
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Thanks for the suggestion, i will go through respective user guide on clockin. Thanks.
https://www.intel.com/content/www/us/en/design-example/714459/intel-arria-10-fpga-an690-pcie-3-0-x8-avalon-memory-mapped-direct-memory-access-dma-with-on-chip-memory-design-example.html
I have one more doubt regarding this example design, I am trying out this design in Quartus 23.4. I see Quartus synth errors wrt some commands in QSF. What is it intended for? Is it okay/safe comment those lines (attached below) and proceed further?
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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Hi,
It is timing fail, if your project requirement does not need strict timing.
As long as the design can be link up correctly, then it can be ignore
Regards,
Wincent_Intel
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Hi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
Regards,
Wincent_Intel
p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.
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Hi
As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.
After 15 days, this thread will be transitioned to community support.
The community users will be able to help you on your follow-up questions.
If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences.
Wincent_Intel
p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

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