PCIe device not detected after programming CVP peripheral core

[LKrup]

I have Reflex Attila Arria 10 GX (chip is Engineering Sample) board with simple PCIe test project on which 'lspci' command shows Altera device. I proceed with instructions in ug_a10_cvp_prop.pdf and after programming peripheral core “lspci” command not showing altera device. I tried programming full .sof and .jic to EPCQL memory and after power off/on and reboot PCIe device still not showing up. Without visible PCIe device altera_cvp kernel module can’t proceed to program logic core and i cant use SignalTap either.

[LKrup]

I attached archived project which i tested it on. Can someone help?

Sorry, by accident I uploaded archived project without "device -> Device and Pin Options-> Configuration via Protocol = Core initialization" option on which I tested with.

[Nathan_R_Intel]

Hie, Your test does not suggest the issue is related to CvP alone. You tried programming full .sof file via .jic and performing cold reboot; this should show PCIe device detected. You need to debug the PCIe linkfurther. I will suggest to connect your Arria 10 board via JTAG to another PC and monitor the LTSSM movement through Signaltap The first step is to understand which LTSSM state is the link stuck at. Regards, Nathan

[LKrup]

I could be wrong but until CVP logic core is not programmed all user logic can't work because it not configured, and Signaltap works on internal block RAM and user logic so I can’t use it. Correct me if I am wrong.

[Nathan_R_Intel]

Hie, I am suggesting to program full .sof file using either JTAG or through Flash (JIC file).. You do not need to use CvP. You can access the signaltap using JTAG connection. Regards, Nathan

[LKrup]

Hi,

My problem was clarified by manufacture which confirmed that problem is caused by ES - "Engineering sample" version of Arria 10.

Also for clarifying Signaltap debugging - even if I programmed Arria 10 by JTAG with .sof bitstream it is still not in user mode and Signaltap cant connect to it. It is only possible while CvP is off, but PCIe worked in that way.

Regards,

Lukasz

[Nathan_R_Intel]

Hi,

Noted that your JTAG issue could be related to ES silicon version. However, I also found that your attached design is not working.  

I verified your cvp_test.qar is not working when ported over to Production device and tested in Arria 10 Development Kit. It cannot link up to LTSSM L0.

Hence, please use Quartus Generated Example design and try it on your board.

To generate the PCIe Example design, you can refer to the following user guide.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-a10-pcie-avmm.pdf

Alternatively, you could try with the reference designs available in Intel Wiki as well.

https://fpgawiki.intel.com/wiki/Reference_Design:_Gen3x8_AVMM_DMA_-_Arria_10

Regards,

Nathan