FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

PCIe interface

Honored Contributor II



I am new to Altera PCIe.  


I am trying to connect the CPRI IP generated with Megacore function to a PCIe interface, which is going to be generated with Qsys. We're using Qsys for the PCIe because we need to use the Avalon-MM PCIe interface so that to connect the Rxm ports of it to the CPU interface of CPRI. 


My question is about PCIe system. I am not sure what components should I use in the Qsys system with PCIe in order (to generate it) to connect it to CPRI IP. 

The structure of CPRI includes the HDLC block, then 2 I/Q data channels of 16 bit integer, CPU interface, an SFP card connected to the PHY layer. 


I saw an example using Avalon-MM PCIe interface, using a DMA controller, memory on-chip, and a Transceiver controller but don't know if I can use it as reference.  

Do you have any hints how is best to configure this Qsys system? How do you suggest to connect the I/Q interface of CPRI to PCIe, what port should we use for that? 



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