PCIe on Cyclone 10 gx dev kit

[KRow]

I bought the cyclone 10 gx dev kit to learn how to implement PCIe.  I do not have large amounts of data to move.  Less the 1Gbs, so Gen 2 or Gen 2 is plenty.  I have tried the examples for this board but I don't understand how I can interface to this with the "User" firmware on the FPGA side.  I need to send and receive data.  Sending from the FPGA needs to be initiated on the FPGA side and sending data from the computer to FPGA needs to be initiated on the computer side. How do I do this.  I am missing some documentation on this?  Is there examples of FPGA send its own data.  This will be used for a data acquisitions system sending and receiving 146 bytes at 200Khz rate.  I want the PCIe for low latency.  Is DMA the way to do this or Streaming?

I normally design in the block schematic type.  For my it is easier to see how things are tied together.  I don't see an example for PCIe in the block schematic format?

Thank you for any help on this.  I am stuck....

Kerry

[ventt]

Hi @KRow,

Thanks for reaching out.

Allow me some time to investigate your issue. I shall come back to you with the findings.

Thanks.

Best Regards,

Ven

[KRow]

Thank you Ven!

[ventt]

Hi @KRow,

You may use either DMA or streaming for data transfer. Note that with DMA, the data transfer occurs without the intervention of the CPU.

We have PCIe Gen 2x4 Avalon Streaming and Gen 2x4 DMA Design Example available in our FPGA Design Store:

1. PCIe Gen 2x4 Avalon Streaming: https://www.intel.com/content/www/us/en/design-example/714943/intel-cyclone-10-gx-fpga-pcie-2-0-x4-avalon-streaming-design-example.html

2. PCIe Gen 2x4 DMA Design Example: https://www.intel.com/content/www/us/en/design-example/714945/intel-cyclone-10-gx-fpga-pcie-2-0-x4-dma-design-example.html

You may follow the design example user guide above to install the driver and run the application.

We do not have the PCIe design example in the block schematic type.

Additionally, starting from the Quartus® Prime Pro Edition software version 23.3, the compiler cannot synthesize schematic Block Design File (.bdf).

Quartus® Prime Pro Edition User Guide Getting Started: https://www.intel.com/content/www/us/en/docs/programmable/683463/24-1/converting-symbolic-bdf-files-to-acceptable.html

Typically, PCIe design examples are built from the parameterizable IP cores in which you can use the IP Catalog (Tools > IP Catalog) to instantiate the PCIe IP core. You may notice in these PCIe design examples, the PCIe IP cores are usually integrated with other IP components to create a functional design. The IP components are then instantiated and wrapped in a top-level module or Qsys file through Platform Designer. To see the interconnection of the IP components in the design example, 

1. You may open the Qsys file and view it in Platform Design. 

Quartus® Prime Pro Edition User Guide Platform Designer: https://www.intel.com/content/www/us/en/docs/programmable/683609/24-1/creating-a-system-with.html

2. Alternatively, you may open the RTL Viewer (Tools > Netlist Viewers > RTL Viewer) after running Analysis & Synthesis to visualize the connections between blocks in the PCIe design example.

Quartus® Prime Pro Edition User Guide Design Compilation: https://www.intel.com/content/www/us/en/docs/programmable/683236/24-1/exploring-the-rtl-analyzer.html

Thanks.

Best Regards,

Ven

[KRow]

Thank you, however I still do not understand how to initiate a transfer or read from the FPGA side.  These examples only have the computer side requesting reads and writes.  How does the FPGA request read and writes?  Am I missing something?  What do I use on the FPGA side to do this?  Still confused.

Thank you,

Kerry

[KRow]

Also I want PCIe for low latency to transfer small chunks of data (146 bytes) in both direction.  I am hoping for latency to be less than 1us.  Is this possible with PCIe?  If not what kind of numbers should I expect?

Thank you,

Kerry

[ventt]

Hi @KRow,

Yes, these design examples initiate the read/write DMA from the host side. Unfortunately, we do not have design examples where the read/write DMA is initiated from the FPGA side.

May I ask what specific latency you are measuring?

We do not have the information on the internal latency of the PCIe Hard IP. The achievable latency will depend on the specific implementation of the PCIe interface.

Thanks.

Best Regards,

Ven

[ventt]

Hi @KRow,

May I know if you have further inquiries on this thread?

Thanks.

Best Regards,

Ven

[ventt]

Hi @KRow,

We have not received any response from you to our previous reply. Please login to ‘https://supporttickets.intel.com’, view details of the desired request, and post a feed/response within the next 15 days to allow me to continue to support you.

After 15 days, this thread will be transitioned to community support.

The community users will be able to help you with your follow-up questions.

Thanks.

Best Regards,

Ven

p/s: If any answers from the community or Intel support are helpful, please feel free to mark them as solutions, give them kudos, and rate the survey 4/5.

[MinzhiWang]

Could i ask question her? I just want to know whether user can implement PCIe IP without using QSYS? You know, not every user familiy with QSYS.