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PCIe - refclk connection

Altera_Forum
Honored Contributor II
878 Views

When implementing PCIe using Qsys on a Cyclone IV GX, should there be a PLL between the refclk pin (100 MHz from connector) and the PCIe IP block? Reference designs do not seem to have one. When I compile without a PLL, I get a critical warning: 

 

Critical Warning: PLL "...|altpll:pll0|altpll_nn81:auto_generated|pll1" input clock inclk[0] may have reduced jitter performance because it is fed by a non-dedicated input 

 

I have refclk routed to a dedicated clock input, and is set as HCSL.
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Altera_Forum
Honored Contributor II
126 Views

I'm targeting a Stratix IV but it's probably the same. The IP instantiates it's own plls so I run the clock input from the pins to the Ip block without a pll. Make sure your clock input in on a clock pin.

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