PCIe with DMA Memory Sizing

[Aflop]

Background :

I am currently using the Arria 10 GX Devkit in preparation for a similar custom board. I have adapted the PCIe Avalon-MM DMA example which Intel provides and come up with a custom design which fits my needs in the moment. I am using Quartus 19.3 pro.

Problem :

The memory sector sizes which are returned when I run 'lspci' do not match those which I set in Platform Designer. 

I have attached "pd_component" which shows the overall design of the platform designer component. 

I have also attached "lspci_output" which shows what the command returns when the devkit is slotted in. 

The table below shows the settings I input into platform designer and the lspci reported size

Bar#	Data Width	Total Memory(B)	Base	End	lspci
2	32	32000	0x0000	0x7cff	32K
3	8	5000	0x8000	0x9387	64K
4	32	4000	0xa000	0xaf9f	64K
5	256	1024	0xb000	0xb3ff	64K

Question :

How to I ensure the 'lspci' command returns the correct sizes of these memory sectors?

Thank you for your help.

[RongYuan]

Hi,

The BAR2 requires 32KB so that size is assigned to this BAR.

Though BAR3 requires only 5KB, a 64KB is assigned to this BAR because of the END addr 0x9387. Similar situation to BAR4 and BAR5.

Regards,

Rong

[RongYuan]

Any further questions?

[Aflop]

I need the lspci command to return the correct sizes of the memory BARs. Lets say I have 3 memory regions of 4KB how would I align these in memory such that lspci returns 4K for their respective sizes?

[RongYuan]

For these 3 BARs, you assign addr 0x0-0xfff each in qsys.

Regards,

Rong

[Aflop]

Assigning the address 0x0-0xfff for each on-chip RAM will result in an error because you are mapping 3 different RAM modules to the same memory region. Attached is a picture of the error. 

To clarify there is a previous project which has different memory modules mapped to different regions and the lspci command returns the correct sizing of these BARs, i.e. there is a 4K BAR not mapped to 0x0-0xfff. Unfortunately this project was done in AHDL and I do not have the time to decode it. 

[RongYuan]

If you want multiple Bars to access one on-chip mem, please try AVMM Pipeline Bridge IP. You can define your address width there.

Regards,

Rong

[Aflop]

This is not the accepted solution. I already have multiple BARs. I never said I wanted them to access one on-chip mem. Maybe it is the accepted solution for YOUR problem but it is not what I asked.

I have multiple BARs access multiple on-chip Mem and it is working fine other than the lspci command does not reflect the correct size. I have moved on to other problems of more importance now. When I have time to investigate this again I will.