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Altera_Forum
Honored Contributor I
911 Views

PFL implementation and CFI interface on STRATIX4 design

I am using a the same design used in the reference board of stratix4 GX for the configuration interface of the FPGA. The configuration mechanism is implemented in a MAXII device (2210F256) and a flash device (PC48F4400). The PFL implemented in the MAXII is the full version (flash programming and FPGA configuration) thrue a FPP interface. When the MaxII is loaded the flash memory is recognized and it is possible to launch a programming cycle of the flash memory. This last is then detected as a succesfull step by the quartus programmer but the "verify check" with the programmer is detected as failed. 

 

I have perfomed a flash reading with the "examine" option and recorded the pof file to compare it with my initial pof file. A file compare tools show me few differences in several part of the memory contents. Few blocks of 64 bytes are stuck at 0xFF. 

 

I have check the PFL implementation and all parameters seems to be in line with the flash characteristics and the pof file. I haven't any more idea to investigate in this problems. Have you ever met this type of problems or do you have an idea on my problem ? 

 

Best regards 

Philippe
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4 Replies
Altera_Forum
Honored Contributor I
49 Views

Hi Philippe, 

 

I have the same PFL configuration that you have described and I am experiencing the same problem where the FLASH programming completes but the verification fails. Did you find a resolution for your problem? 

 

Best Regards, 

Jody
Altera_Forum
Honored Contributor I
49 Views

Yes I found it, 

 

We used the same MAXII design supplied by ALTERA with one of SIV GX design reference board. A watchdog function is intantiated in this design and this last was appropriates for a SIV230GX but not for SIV530GX. 

 

To analyse this issue I have compliled my 2 projects (230 & 530) to obtain rbf files. For the 230 devive the rbf flie size is about 10 MB and for 530 devive the rbf flie size is about 20 MB. Then I have deducted that the number of DCLK cycle should have been proportionnal ... it wasn't the case. By instrumenting the PFL signals I have identifed that the configuration cycle of SIV530GX was interupted by another function in the design ... it was the watchdog. I have modified the watchdog counter value to solve this issue. 

 

Best regards, 

Philippe
Altera_Forum
Honored Contributor I
49 Views

Hi Philippe, 

 

Thanks for your response! I don't have a watchdog timer in my design, so it looks like we have different problems - I will keep looking. 

 

Best Regards, 

Jody
Altera_Forum
Honored Contributor I
49 Views

Probably not too helpful for the original posters but may help anyone in the future. 

I had the exact same problem. 

The flash (PC48f4400) isn't on Altera's list of supported CFI flash. Thus you have to define it in the Altera Quartus Programmer, otherwise, it won't know the proper timings of this flash device and result in incorrect operation. 

 

To define it: 

Programmer -> Edit -> Define CFI Flash Device 

 

You should be able to find all the parameters you need in the device datasheet. 

All you have to do is define it correctly, when the Quartus Programmer detects a CFI flash device that matches the manufacturer and device id you provided, it will use the device you defined. 

You can tell it works because during programming in the console window, it will indicate the name of your defined device (PC48F4400 in my case) during programming (i.e. "Info: Programming status: verify on flash device 1 (PC48F4400) at device chain position 2")
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