During FPGA configuration from MAX II with parallel flash by Intel P33 series
if I don't want to use PFL IP on CPLD. I am using my own HDL codes for fpga configuration
start pages definition mention is in my CPLD HDL codes
my Question is what will be option bits ?
we have to define option bits during SOF to POF conversation ?
or what all should be zeros
kindly help us
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The option bit is meant for the PFL IP. If you used your own codes, when generate from .sof to .pof, Quartus will generate the bit for you. Can you clarify why need to know the option bits?
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