PFL not use

[nome]

Hello

During FPGA configuration from MAX II with  parallel flash by Intel P33 series 

if I don't want to use  PFL IP on CPLD. I am using my own HDL codes for fpga configuration 

start pages definition mention is in my CPLD HDL codes   

my Question is what will be option bits ?

we have to define option bits during SOF to POF conversation ?

or what all should be zeros  

kindly help us 

Thanks

[nome]

Hello

still waiting.......

Thanks

Nome

[NurAiman_M_Intel]

Hi,

Thank you for contacting Intel community.

The option bit is meant for the PFL IP. If you used your own codes, when generate from .sof to .pof, Quartus will generate the bit for you. Can you clarify why need to know the option bits?

Regards,

Aiman

[NurAiman_M_Intel]

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you