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PLL Reconfiguration read of PLL registers

I have implemented a PLL outside of the Qsys and included an Altera PLL Reconfig component within my Qsys system. I have exported the reconfig_to_pll and the reconfig_from_pll to my external PLL. I have compiled the design with a default 25MHz clock within the PLL. I tried to read the parameters of the PLL via my Altera PLL Reconfig component however I have so far only received ZEROES ! Please could someone help me ?

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Re: PLL Reconfiguration read of PLL registers

Hi Shmuel

 

Thanks for your inquiry. Allow me to understand your issue. May I know which device you are using and if possible, can you attach more details or share the design?

 

Thanks.

Eng Wei

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Re: PLL Reconfiguration read of PLL registers

Dear Eng Wei,

 

Thanks for getting back to me.

 

I am using a Cyclone V. I have compiled a design with a PLL that has been set to 25MHz. I have also included a Qsys system where the NIOS has been connected to a Altera PLL Reconfig component. The reconfig_to_pll and reconfig_from_pll signals have both been exported and connected to the external PLL in accordance to AN661. I have also generated a .mif file that will allow me to reconfigure the PLL to 125MHz. We initially wrote firmware that would just go ahead and read the Reconfiguration Registers in order to read the current values that were compiled with the design. Our plan was once we have confirmed this then we were going to re-program the PLL and then re-read the register and check the new values (as well as see the change of the clock frequency via a scope). When we tried this initial read of the reconfiguration Registers we unfortunately we only read zero values. However the clock in fact was measured as 25MHz as expected. We performed a regular NIOS read from the registers based upon the "Table 2: Fractional PLL Dynamic Reconfiguration Registers and Settings" found in the AN661. Is there something we are doing wrong ?

 

Thanks again for all your help

 

Bets regards

 

Shmuel

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Re: PLL Reconfiguration read of PLL registers

Hi Shmuel

 

There is a sample design (with .qar) mentioned in the section "1.4.6. Design Example 5: .mif Streaming Reconfiguration" in the doc https://www.intel.com/content/www/us/en/programmable/documentation/mcn1424769382940.html#mcn14256323...

 

You can take the example and cross check with your design implementation.

 

Thanks.

Eng Wei

 

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Moderator
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Re: PLL Reconfiguration read of PLL registers

Hi Shmuel

 

Do you still facing any issue after referring to the sample design?

 

Thanks.

Eng Wei

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Moderator
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Re: PLL Reconfiguration read of PLL registers

 

Hi Shmuel

We do not receive any response from you to the previous sample design that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

 

Eng Wei

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