I have implemented a PLL outside of the Qsys and included an Altera PLL Reconfig component within my Qsys system. I have exported the reconfig_to_pll and the reconfig_from_pll to my external PLL. I have compiled the design with a default 25MHz clock within the PLL. I tried to read the parameters of the PLL via my Altera PLL Reconfig component however I have so far only received ZEROES ! Please could someone help me ?
Thanks for your inquiry. Allow me to understand your issue. May I know which device you are using and if possible, can you attach more details or share the design?
Dear Eng Wei,
Thanks for getting back to me.
I am using a Cyclone V. I have compiled a design with a PLL that has been set to 25MHz. I have also included a Qsys system where the NIOS has been connected to a Altera PLL Reconfig component. The reconfig_to_pll and reconfig_from_pll signals have both been exported and connected to the external PLL in accordance to AN661. I have also generated a .mif file that will allow me to reconfigure the PLL to 125MHz. We initially wrote firmware that would just go ahead and read the Reconfiguration Registers in order to read the current values that were compiled with the design. Our plan was once we have confirmed this then we were going to re-program the PLL and then re-read the register and check the new values (as well as see the change of the clock frequency via a scope). When we tried this initial read of the reconfiguration Registers we unfortunately we only read zero values. However the clock in fact was measured as 25MHz as expected. We performed a regular NIOS read from the registers based upon the "Table 2: Fractional PLL Dynamic Reconfiguration Registers and Settings" found in the AN661. Is there something we are doing wrong ?
Thanks again for all your help
There is a sample design (with .qar) mentioned in the section "1.4.6. Design Example 5: .mif Streaming Reconfiguration" in the doc https://www.intel.com/content/www/us/en/programmable/documentation/mcn1424769382940.html#mcn14256323...
You can take the example and cross check with your design implementation.
We do not receive any response from you to the previous sample design that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
I am having the same issue. I too am using a Cyclone V, but in my case an SOC part. Both the pll reconfig and pll themselves are part of the same Qsys system. The pll configures to the expected output frequencies on power-up from the .sof. The pll reconfig avalon interface is connected to the ARM axi master, and I am able to read/write to other peripherals of the system. I only read 0's from all pll reconfig registers however, and am not able to change write registers. AN 661 shows the the pll reconfig and pll itself driven from the same clock, though I do not know if this is required. I have tried multiple clocking configurations including driving them from the same clock with no change. I have so far only driven their reset inputs from the same source. Don't know if this is related. It's acting like the pll reconfig peripheral is held in reset, though the pll is obviously not reset with outputs clocks present and they are driven from the same reset source.
More information for my case:
I actually have 2 PLL reconfig blocks in my Qsys project, obviously for 2 different PLLs. I was attempting to use MIF file streaming to reprogram the PLLs for different configurations, creating a merged PLL MIF file for each using the merge_mif Tcl script as described in AN 661. I just tried disabling the MIF streaming in the configuration of the PLL reconfig blocks. Low and behold after disabling it for one of the blocks I am now able to read/write to its registers. Curiously, for the other reconfig PLL block now when I attempt to do a read from the register space the read hangs (to be specific, I'm using the memtool function of Linux running on the SOC's ARM). Before the read returned but returned all zero's. The second reconfig PLL block is connected to a PLL that I also configured to use the dynamic phase shift ports at the same time, which to be fair the IP configuration tool warns is not recommended. Perhaps the simultaneous use of mif streaming and dynamic phase shift port is related to the hanging of the register read operation of the reconfig block, though this seems unfriendly.
And yet some more information about my case:
The Pll Reconfig block that hangs on attempt to read registers is connected to a PLL being used with an LVDS RX block in external PLL mode. I see errata from a few years back about using the Pll reconfig block with LVDS TX in Cyclone V with Quartus v14. I'm using Quartus Prime 18.1, and as I said with an LVDS RX. The LVDS rx does receive data ok when configured from the .sof, even with the PLL reconfig block connected and with or without .mif initialization enabled. Just can't reprogram it for a different data rate using Pll reconfig IP.