FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5988 Discussions

PLL does not lock anymore after connecting DDR3

Honored Contributor II



I'm designing a system with an NIOS and a DDR3 HMI.  


The fist shot was to implement the NIOS with internal RAM and a PLL. The PLL generates 50MHz from my connected 25MHz crystal. This setup works fine, and the Hello World from NIOS works as well. 



Now I would like to have the DDR3 SDRAM running. But since I intergated the DDR3, my PLL doesn't lock anymore!! 


The refclock for the DDR3 is directly from the 25MHz crystal and i can see the 355MHz AFI is coming out (with a scope). 


I tried to connect the PLL for the Nios to 

-directly the same 25MHz-Pin as the DDR3 

-At the AFI 355MHz output 


But the PLL does not lock! Not at 50MHz or at 71MHz which would be 355/5 


Thanks for any advice
0 Kudos
4 Replies
Honored Contributor II

Are you able to simulate your design to see if same issue there?

Honored Contributor II

Well the problem was that the RREF pin. After connecting it correctly it worked: 


Cyclone® V Device Family Pin Connection Guidelines: 

If any PLL, REFCLK pin, or transceiver channel is used, you must connect each RREF pin on that 

side of the device through its own individual 2.0-kΩ +/- 1% resistor to GND. Otherwise, you may 

connect each RREF pin on that side of the device directly to GND. In the PCB layout, the trace 

from this pin to the resistor needs to be routed so that it avoids any aggressor signals.
Honored Contributor II

Glad to hear that you have managed to resolve the issue. Thanks for sharing the solution as well.

Honored Contributor II

Thank you for the info on the fix.