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5950 Discussions

PLL driving ALTCLKCTRL routing CYCLONE IV E

Altera_Forum
Honored Contributor II
845 Views

Hi Folks, 

 

-Cyclone IV E 

 

I have a PLL whose output I feed to an ALTCLKCTRL IP with an enable, the output of which feeds a CLK output pin on the device. 

 

When compiling I get the following warning: 

 

warning (15064): pll "altpll1:b2v_inst1|altpll:altpll_component|altpll1_altpll1:auto_generated|pll1" output port clk[0] feeds output pin "sma_clkout~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. use pll dedicated clock outputs to ensure jitter performance 

 

 

I dont see this warning when I leave out the CLKCTRL and therefore just feed the output directly to an PLL output (SMA_CLKOUT in above msg) 

 

What do I need to do to the routing to ensure that i can pass the PLL output through the CLKCTRL and to the PLL output pin without reducing performance? 

 

I have had a look at the assignments page, but I am a little uncertain what I need to set up, playing around with it just seems to result in unknown nodes (question marks)... 

 

many thanks for any advice 

David
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1 Reply
Altera_Forum
Honored Contributor II
115 Views

I think I may have stumbled upon something... 

 

I have selected the CLKCTRL such that it is not driving the Global clock network but an external clock output. But this generates a different warning... 

 

Warning (10651): VHDL Assertion Statement at PULSEPICKER.vhd(92): assertion is false - report "MGL_INTERNAL_WARNING: ( The parameter value is not one of the pre-specified values in the value list.) altclkctrl|stratixii_clkctrl inst clkctrl1|ena_register_mode The value assigned is double register and the valid value list is none|falling edge" (WARNING) 

 

SHould I be worried about this, if so what do i do about it? 

 

thanks again 

D
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