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Altera_Forum
Honored Contributor I
730 Views

PLL's error on ARRIA II GX

I am currently using ARRIA II GX device on the SDI project. The device 

has 4 avilable PLL's to use. I ran into comlilation error which indicates 

somewhat like I don't have enough PLL ??? despite the fact that there 

are 4 available !!! Could you expert take a look a the error message below 

to see what are the problems? 

 

Thanks in advance. 

 

JIMMY 

 

 

 

error: can't place pll "test_pll:inst9|altpll:altpll_component|test_pll_altpll:auto_generated|pll1" in target device due to device constraints 

 

error: can't place pll "test_pll:inst9|altpll:altpll_component|test_pll_altpll:auto_generated|pll1" in pll location pll_1 because location is already occupied by node "altpll_1to1:inst105|altpll:altpll_component|altpll_99c2:auto_generated|pll1" 

 

error: pll "test_pll:inst9|altpll:altpll_component|test_pll_altpll:auto_generated|pll1" can't be placed at location pll_2. this location cannot route to the gxb pll cascade network, which is necessary to drive the following gxb pll atom(s). 

 

error: pll "test_pll:inst9|altpll:altpll_component|test_pll_altpll:auto_generated|pll1" can't be placed at location pll_3. this location cannot route to the gxb pll cascade network, which is necessary to drive the following gxb pll atom(s).
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2 Replies
Altera_Forum
Honored Contributor I
33 Views

Seems that all depends on other factor. 

 

1)Error: Can't place PLL "test_pll:inst9|altpll:altpll_component|test_pll_altpll:auto_generated|pll1" in target device due to device constraints 

 

It should be if you've try to set the PLL in a location that is not compatible, or if your CLOCK INPUT PIN is phisically attached not to the PLL you've set to use. 

 

2)Error: PLL "test_pll:inst9|altpll:altpll_component|test_pll_a ltpll:auto_generated|pll1" can't be placed at location PLL_2. This location cannot route to the GXB PLL cascade network, which is necessary to drive the following GXB PLL atom(s). 

 

Error: PLL "test_pll:inst9|altpll:altpll_component|test_pll_a ltpll:auto_generated|pll1" can't be placed at location PLL_3. This location cannot route to the GXB PLL cascade network, which is necessary to drive the following GXB PLL atom(s). 

 

From the message it seems that you're using one of these PLL in order to generate clocks for GXB, but for example you cannot use PLL that are not on the same side of GXB. (or at least on a Stratix IV this is a limitation). 

 

3) 

Error: Can't place PLL "test_pll:inst9|altpll:altpll_component|test_pll_a ltpll:auto_generated|pll1" in PLL location PLL_1 because location is already occupied by node "altpll_1to1:inst105|altpll:altpll_component|altpl l_99c2:auto_generated|pll1" 

 

Seems that you're trying to use the same location that is used by the other PLL. 

 

 

Unfortunatly I cannot be more precise cause I do not use Arria and I've no time to look at documentation for yourself. 

Try to have a look at Arria Manual in order to get informed of where are the PLL and which ones can be routed to GXB. 

 

Good luck
Altera_Forum
Honored Contributor I
33 Views

 

--- Quote Start ---  

Seems that all depends on other factor. 

 

1)Error: Can't place PLL "test_pll:inst9|altpll:altpll_component|test_pll_altpll:auto_generated|pll1" in target device due to device constraints 

 

It should be if you've try to set the PLL in a location that is not compatible, or if your CLOCK INPUT PIN is phisically attached not to the PLL you've set to use. 

 

Good luck 

--- Quote End ---  

 

 

Hi Darkwave,  

From Pin Planner, I know which pins are connected to PLL, for example, PIN_AA) PLL_CLKOUT1n, as I am trying to set DDR2, I didn't place PLL manually. So, based on what you said, cause# 1 is out of question since it is automatically placed, therefore, cause# 2, my ref_clk wich is constrained by my .sdc to be 100MHz. 

 

How do I know where my PLL is? and how to connect them?
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