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Honored Contributor I

POS-PHY LEVEL 4 (SPI4.2) Loopback Reference Design

Recently, while browsing around Altera website, I came across a very useful site for reference that gives an example on how to use the Altera SPI-4.2 protocol to perform a simple transmit and receive loopback on the Altera development kit. Indeed, it provides users with a good overview on how to set the parameter settings and makes it work on the Altera board. The SPI-4.2 reference design that I stated here can be obtained at the following link: (  


From the webpage, you can download the Quartus II archive project ZIP file to implement it on Stratix IV GX developement board or Stratix III development board respectively. If you want to implement the design immediately without going through recompilation of the project, you can download the SOF provided directly to the development board. However, one thing that you need to make sure is to use the downloaded SOF that matches the FPGA on your SIV board. There are 2 SOF files provided for the SIV GX zip package download, they are: top_ep4sgx230kf40c2.sof and top_ep4sgx230kf40c3es.sof. There is also a simple README file in the downloadable stratix4-spi4-loop-back-on-development-board ZIP package that illustrates the steps to test it and discusses the results of implementation.  


Here, I would also like to share something that is not available from that website with everyone. By a fortuitous luck, I managed to get a copy of the Application Note from Altera factory. The Application Note describes the loopback design modules in detail (with architecture block diagrams), provides SPI-4.2 parameter settings for transmit and receive core and Modelsim simulation testbench. A Modelsim simulation project zip package is provided together with the Application Note. So I am attaching the Simulation zip package and the Application Note here for anyone who is interested in using Altera SPI-4.2 core to benefit from.
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