hey,
I was creating the Parallel Flash Loader IP by Quartus MegaFunction.
I integrated this IP in the Top design file( add the IP's ports, declare the IP, mapping the IP to the Top's port). Then I mapped the ports to the FPGA's I/O and I got problems in Quartus (in the Fitter stage) about multiple pins assignments for these mapping routes. they collides with reserved Altera pins:
Error(176310): can't place multiple pins assigned to pin location Pin_E2 (IOPAD_X0_Y36_N7)
Info(176311) : pin flash_nce is assigned to pin location Pin_E2
Info(176311) : pin ~AlLTERA_FLASH_nCE_nCSO~ is assigned to pin location Pin_E2
this is the component ports:
component parallel_flash_loader is
port (
pfl_flash_access_granted: in std_logic;
pfl_nreset:in std_logic;
flash_addr: out std_logic_vector(22 downto 0);
flash_data:inout std_logic_vector(15 downto 0);
flash_nce: out std_logic;
flash_noe: out std_logic;
flash_nwe:out std_logic;
pfl_flash_access_request:out std_logic
);
end component parallel_flash_loader ;
I need some help here, thank you
