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Valued Contributor III

Parallel Flash Loader Option Bits



I would like to use a Parallel Flash Loader inside a MAXII CPLD to configure a Stratix III device. 

The manual (AN386) suggest how to use the parallel flash loader also to program the flash. I would not like to program the CPLD once only to configure the flash because it has a limited number of guaranteed program cycles. I would like to use some software inside the Nios II processor in the FPGA to configure flash. 

I am already able to write a RBF into the flash (using u-boot for example) but I have some problems to define the Option bits for the PFL. 

At page 6 of AN386 I see that bits 0-11 of the address are all set to zero and not stored. That's fine... but next page has a figure with bits 0-12 ignored. 

Another confusing bit is the bit 0 of the third byte (the one which configures the Page End Address). Is it a don't care? 


if anyone has already some experience in such kind of configuration... 


Thanks a lot, 

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